eppl_avr8_internals.h

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/*
   Copyright (c) 2013, Radoslaw Koppel
   All rights reserved.

   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
      
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.

    - Neither the name of the copyright holders nor the
      names of its contributors may be used to endorse or promote products
      derived from this software without specific prior written permission.

   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER BE LIABLE FOR ANY
   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef EPPL_AVR8_INTERNALS_H_INCLUDED
#define EPPL_AVR8_INTERNALS_H_INCLUDED

#define EPPL_avr8_CPORTREG(reg, cportnr) (xEPPL_avr8_CPORTREG(reg, cportnr))

#define xEPPL_avr8_CPORTREG(reg, cportnr) EPPL_p##reg##cportnr

#define EPPL_avr8_PORTREG(reg, portnr) \
    (((portnr) == 0) ? EPPL_avr8_CPORTREG(reg, 0) : \
    (((portnr) == 1) ? EPPL_avr8_CPORTREG(reg, 1) : \
    (((portnr) == 2) ? EPPL_avr8_CPORTREG(reg, 2) : \
    (((portnr) == 3) ? EPPL_avr8_CPORTREG(reg, 3) : \
    (((portnr) == 4) ? EPPL_avr8_CPORTREG(reg, 4) : \
    (((portnr) == 5) ? EPPL_avr8_CPORTREG(reg, 5) : \
    (((portnr) == 6) ? EPPL_avr8_CPORTREG(reg, 6) : \
    (((portnr) == 7) ? EPPL_avr8_CPORTREG(reg, 7) : \
    (((portnr) == 8) ? EPPL_avr8_CPORTREG(reg, 8) : \
    (((portnr) == 9) ? EPPL_avr8_CPORTREG(reg, 9) : \
    (((portnr) == 10) ? EPPL_avr8_CPORTREG(reg, 10) : \
    (((portnr) == 11) ? EPPL_avr8_CPORTREG(reg, 11) : \
    ((volatile uint8_t*)NULL) \
    ))))))))))))

   #ifdef PORTA
      #define EPPL_pPORT0 &PORTA
      #define EPPL_pPIN0 &PINA
      #define EPPL_pDDR0 &DDRA
   #else
      #define EPPL_pPORT0 ((uint8_t*)NULL)
      #define EPPL_pPIN0 ((uint8_t*)NULL)
      #define EPPL_pDDR0 ((uint8_t*)NULL)
   #endif

   #ifdef PORTB
      #define EPPL_pPORT1 &PORTB
      #define EPPL_pPIN1 &PINB
      #define EPPL_pDDR1 &DDRB
   #else
      #define EPPL_pPORT1 ((uint8_t*)NULL)
      #define EPPL_pPIN1 ((uint8_t*)NULL)
      #define EPPL_pDDR1 ((uint8_t*)NULL)
   #endif

   #ifdef PORTC
      #define EPPL_pPORT2 &PORTC
      #define EPPL_pPIN2 &PINC
      #define EPPL_pDDR2 &DDRC
   #else
      #define EPPL_pPORT2 ((uint8_t*)NULL)
      #define EPPL_pPIN2 ((uint8_t*)NULL)
      #define EPPL_pDDR2 ((uint8_t*)NULL)
   #endif

   #ifdef PORTD
      #define EPPL_pPORT3 &PORTD
      #define EPPL_pPIN3 &PIND
      #define EPPL_pDDR3 &DDRD
   #else
      #define EPPL_pPORT3 ((uint8_t*)NULL)
      #define EPPL_pPIN3 ((uint8_t*)NULL)
      #define EPPL_pDDR3 ((uint8_t*)NULL)
   #endif

   #ifdef PORTE
      #define EPPL_pPORT4 &PORTE
      #define EPPL_pPIN4 &PINE
      #define EPPL_pDDR4 &DDRE
   #else
      #define EPPL_pPORT4 ((uint8_t*)NULL)
      #define EPPL_pPIN4 ((uint8_t*)NULL)
      #define EPPL_pDDR4 ((uint8_t*)NULL)
   #endif

   #ifdef PORTF
      #define EPPL_pPORT5 &PORTF
      #define EPPL_pPIN5 &PINF
      #define EPPL_pDDR5 &DDRF
   #else
      #define EPPL_pPORT5 ((uint8_t*)NULL)
      #define EPPL_pPIN5 ((uint8_t*)NULL)
      #define EPPL_pDDR5 ((uint8_t*)NULL)
   #endif

   #ifdef PORTG
      #define EPPL_pPORT6 &PORTG
      #define EPPL_pPIN6 &PING
      #define EPPL_pDDR6 &DDRG
   #else
      #define EPPL_pPORT6 ((uint8_t*)NULL)
      #define EPPL_pPIN6 ((uint8_t*)NULL)
      #define EPPL_pDDR6 ((uint8_t*)NULL)
   #endif

   #ifdef PORTH
      #define EPPL_pPORT7 &PORTH
      #define EPPL_pPIN7 &PINH
      #define EPPL_pDDR7 &DDRH
   #else
      #define EPPL_pPORT7 ((uint8_t*)NULL)
      #define EPPL_pPIN7 ((uint8_t*)NULL)
      #define EPPL_pDDR7 ((uint8_t*)NULL)
   #endif

   #ifdef PORTI
      #define EPPL_pPORT8 &PORTI
      #define EPPL_pPIN8 &PINI
      #define EPPL_pDDR8 &DDRI
   #else
      #define EPPL_pPORT8 ((uint8_t*)NULL)
      #define EPPL_pPIN8 ((uint8_t*)NULL)
      #define EPPL_pDDR8 ((uint8_t*)NULL)
   #endif

   #ifdef PORTJ
      #define EPPL_pPORT9 &PORTJ
      #define EPPL_pPIN9 &PINJ
      #define EPPL_pDDR9 &DDRJ
   #else
      #define EPPL_pPORT9 ((uint8_t*)NULL)
      #define EPPL_pPIN9 ((uint8_t*)NULL)
      #define EPPL_pDDR9 ((uint8_t*)NULL)
   #endif

   #ifdef PORTK
      #define EPPL_pPORT10 &PORTK
      #define EPPL_pPIN10 &PINK
      #define EPPL_pDDR10 &DDRK
   #else
      #define EPPL_pPORT10 ((uint8_t*)NULL)
      #define EPPL_pPIN10 ((uint8_t*)NULL)
      #define EPPL_pDDR10 ((uint8_t*)NULL)
   #endif

   #ifdef PORTL
      #define EPPL_pPORT11 &PORTL
      #define EPPL_pPIN11 &PINL
      #define EPPL_pDDR11 &DDRL
   #else
      #define EPPL_pPORT11 ((uint8_t*)NULL)
      #define EPPL_pPIN11 ((uint8_t*)NULL)
      #define EPPL_pDDR11 ((uint8_t*)NULL)
   #endif

#define EPPL_avr8_CheckRegSupportsBit(regptr) ( ((int)(regptr)) - __SFR_OFFSET < 32 )



   #define EPPL_avr8_modeGet(ms)  ((ms) & EPPL_mode_mask)

   #define EPPL_avr8_stateGet(ms) ((ms) & EPPL_outSet_mask)
   
   #define EPPL_avr8_mode_knownDDR(m) ( \
 \
      (EPPL_avr8_modeGet(m) == EPPL_mode_outPP) || \
 \
         ( ((m) & EPPL_mode_flag) && \
            ( !((m) & EPPL_mode_out) || \
 \
            ((m) & EPPL_outSet_flag) ) \
         ) \
      )
      
   #define EPPL_avr8_mode_knownPORT(m) ( \
 \
      (EPPL_avr8_modeGet(m) == EPPL_mode_outOC) || \
 \
      ((m) & EPPL_outSet_flag) )
      
   #define EPPL_avr8_mode_valueDDR(m) ( ( \
      (EPPL_avr8_modeGet(m) == EPPL_mode_outPP) || \
      (EPPL_avr8_mapOutModify_DDR(m) && ( \
         (EPPL_avr8_mapOutNegate_DDR(m) && (EPPL_avr8_stateGet(m) == EPPL_outSet_0)) || \
         (!EPPL_avr8_mapOutNegate_DDR(m) && (EPPL_avr8_stateGet(m) == EPPL_outSet_1)) \
         ) \
      ) \
      ) ? 1 : 0 )

   #define EPPL_avr8_mode_valuePORT(m) ( ( \
      ((EPPL_avr8_mapOutModify_PORT(m) || !(EPPL_avr8_modeGet(m) & EPPL_mode_out)) && ( \
         (EPPL_avr8_mapOutNegate_PORT(m) && (EPPL_avr8_stateGet(m) == EPPL_outSet_0)) || \
         (!EPPL_avr8_mapOutNegate_PORT(m) && (EPPL_avr8_stateGet(m) == EPPL_outSet_1)) \
         ) \
      )\
      ) ? 1 : 0 )

   #define EPPL_avr8_mode_modifiedReg(reg, from, to) ( \
         ( EPPL_avr8_mode_known##reg(from) && EPPL_avr8_mode_known##reg(to) && (EPPL_avr8_mode_value##reg(from) != EPPL_avr8_mode_value##reg(to)) ) || \
         ( !EPPL_avr8_mode_known##reg(from) && EPPL_avr8_mode_known##reg(to) ) \
      )

#define eppl_avr8_asm_sbi(regptr, bit) \
   __asm__ __volatile__ ( \
      "sbi %0, %1" "\n\t" \
      : \
      : "I" ( ((int)(regptr)) - __SFR_OFFSET ), \
      "I" (bit) \
   )

#define eppl_avr8_asm_cbi(regptr, bit) \
   __asm__ __volatile__ ( \
      "cbi %0, %1" "\n\t" \
      : \
      : "I" ( ((int)(regptr)) - __SFR_OFFSET ), \
      "I" (bit) \
   )

#define EPPL_avr8_checkPinsDescending(...) xEPPL_avr8_checkPinsDescending(__VA_ARGS__, )
#define xEPPL_avr8_checkPinsDescending(pin1, pin2, ...) ( \
   (pin1) >= 0 && (pin2) >= 0 && \
   EPPL_PORTNR(pin1) == EPPL_PORTNR(pin2) && \
   EPPL_PINNR(pin1) == (EPPL_PINNR(pin2) + 1) )

#define EPPL_avr8_LRSH(v, sl, sr) \
   ((uint8_t)(((sl) > (sr)) ? \
      (uint8_t)((v) << ((sl)-(sr))) \
   : \
      (uint8_t)((v) >> ((sr)-(sl))) \
   ))

#define eppl_avr8_asm_bitcpy(dst, dstpos, src, srcpos) \
   __asm__( \
      "bst %[s], %[sb]" "\n\t" \
      "bld %[d], %[db]" "\n\t" \
      :[d]"+r"(dst) \
      :[s]"r"(src), \
       [db]"I" (dstpos), \
       [sb]"I" (srcpos) \
   )


#endif /* EPPL_AVR8_INTERNALS_H_INCLUDED */